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On all instruction cycles, the processor excesses memory at least once, to fetch the instruction, and often one or more additional lines, to fetch operands and/or store results. The rate at which the processor can execute instructions is clearly limited by the memory cycle time. This limitation has in fact been a significant problem because of the persistent mismatch between the processor and main memory speeds. Over the years, processor speed has consistently increased more rapidly than memory access speed. What the designer is faced with is a trade off among speed, cost and size. Ideally ,the main memory should be built with the same technology as that of the processor registers, giving memory cycle times comparable to the processor cycle times. This has always been too expensive as a strategy. The solution is to exploit the principle of locality by providing a small, fast memory between the processor and main memory, namely the cache.
Cache Principle
The cache principle revolves around the idea of giving a memory with fastest speed but with a large size, thereby giving the users a major advantage while deciding for memory requirements according to their respective needs. In cache memory a copy of the main memory portion is kept. During a processor read from the memory, first cache memory is checked for the required word and if it is there the processor retrieves the word. . If not, a block of main memory, consisting of some fixed no. of words is read into the cache and then the word is delivered to the processor. Because of the phenomenon of reference, when a block of data is fetched into the cache to satisfy a single memory reference, it is likely that future references will be to other words in the block. Moreover a cache memory comes at a comparatively less price as that of its other silicon mates.
Cache Design
The key designer issue to be addressed while dealing with virtual memory and disk cache design are:
- Cache size
- Block size
- Mapping function
- Replacement Algorithm
- Write policy
It turns out that reasonably small cache can have a significant impact on performance. Another size issue is that of block size: the unit of data exchanged both cache and main memory. As the block size increases from very small to larger sizes, the hit ratio will at first increase because of the principle of locality: the high probability that data in the vicinity of a referenced word are likely to be referenced in the near future. As the block size increases, more useful data are brought into the cache. However decrease in the hit ratio can be observed with the increase in the block size. Moreover, newly fetched data usage also decreases as compared to the re-usage of data being moved out of the cache.
When a new block of data is read into the cache, the mapping function determines which cache location the block will occupy. The more flexible the mapping functions, the more scope we have to design a replacement algorithm to maximize the hit ratio.
The replacement algorithm chooses within the constraints of the mapping function, which block to replace when a new block is to be loaded into the cache and the cache already had all slots filled with other blocks. We would like to replace the block that is least likely to be needed again in the near future.
If the contents of the block in the cache are altered, then it is necessary to write it back in the main memory before replacing it. The write policy dictates when the memory write operation takes place. At one extreme the writing can occur every time that the block is updated. At the other extreme, the writing occurs only when the block is replaced .The later policy minimizes memory write operation but leaves main memory in an obsolete state .This can interfere with multiple processor operation and with direct memory access by I/O modules.
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